872222-B21 HPE CPU Mezzanine Expansion Riser at discount

872222‑B21 Specifications

HPE DL5x0 Gen10 CPU Mezzanine Board Kit (Expansion Riser)

Manufacturer: Hewlett‑Packard Enterprise (HPE)
Manufacturer Model: 872222‑B21
Product Line: HPE Server Mezzanine Boards
Product Series: DL5x0 Gen10 CPU Mezzanine
Product Type: Expansion Board / CPU Mezzanine Kit
Product Name: HPE DL5x0 Gen10 CPU Mezzanine Board Kit

KEY FEATURES:
Board Type: Server CPU mezzanine expansion board
Compatibility: HPE ProLiant DL560 Gen10 and DL580 Gen10 servers
Supports Additional CPUs: Enables installation of additional CPUs in supported systems
Total PCIe Lanes: ~20 PCI Express lanes for expansion
Expansion Slots: Multiple mezzanine expansion slots (includes x16, x8, x4 lane options)
Maximum Processor Support: Typically supports Intel Xeon Scalable processors (up to four total in full configuration) when combined with appropriate CPU modules and server support
Maximum Memory Support: Up to ~2 TB expanded memory with full CPU and mezzanine configuration

PERFORMANCE:
Processor & Memory Expansion: Allows servers to scale to additional CPU sockets and memory channels beyond the default configuration, improving processing throughput and memory capacity for demanding enterprise workloads
PCIe Bandwidth: Provides high‑speed PCIe connectivity between CPUs and system board for expansion devices

ENVIRONMENTAL & RELIABILITY:
Designed for enterprise 24×7 operation in rack‑mount server environments
Operating Temperature: ~0 °C to 55 °C typical server spec range
Operating Humidity: ~10 % to 90 % non‑condensing typical server range

COMPATIBILITY:
HPE Server Platforms: HPE ProLiant DL560 Gen10 and DL580 Gen10 servers — required for systems that need more than standard dual‑CPU configuration or expanded memory slots
Supported Processor Families: Intel Xeon Scalable CPUs (varies by server and configuration)

PHYSICAL:
Form Factor: Mezzanine board / expansion riser board
Typical Weight: Moderate (~0.7 kg approximate)
Typical Dimensions: Server mezzanine board size (varies by implementation